IEEE 1800TM SystemVerilog is the industry's first unified hardware description and verification language (HDVL) standard. SystemVerilog is a major extension of the established IEEE 1364TM Verilog language. It was developed originally by Accellera to dramatically improve productivity in the design of large gate-count, IP-based, bus-intensive chips. SystemVerilog is targeted primarily at the chip implementation and verification flow, with powerful links to the system-level design flow. Its main extensions over Verilog include:
Support of modeling and verification at the “transaction” level of abstraction. SystemVerilog’s Direct Programming Interface (DPI) enables it to “call” C/C++/SystemC functions, and vice versa. SystemVerilog is thus the first Verilog-based language to enable efficient co-simulation with SystemC blocks – an invaluable link between system level design and chip implementation and verification.
A set of extensions to address advanced design requirements. Examples include – among others – modeling interfaces that greatly accelerate the development of bus-intensive designs; removal of restrictions on module port connections, allowing any data type on each side of the port; extended data types to allow C modeling; enhanced IP protection by nesting modules locally to their parent module and, consequently, not visible to other parts of the design.
A new mechanism to support assertion-based verification (ABV), enabling a “design for verification” methodology. In SystemVerilog, assertion information is built into the language, eliminating the need for the special modules, pragmas or PLI calls used in traditional Verilog. Embedded assertions capture real “design intent” in terms of functionality and constraints, and are verified by simulation before application of any formal or dynamic verification methods. This approach helps to avoid recoding errors, increase test accuracy, simplify the testbench, and enable test reuse. The full controllability and observability of internal circuit nodes afforded by ABV can significantly reduce design debug time. For example, IBM reports a 50% reduction in debug time using this methodology. Very importantly, this controllability and observability will spur the innovation of advanced design and verification tools, with one area of interest being assertion-based synthesis.
New features to support hardware models and testbenches that utilize object-oriented techniques – testbenches that are eminently re-usable. For example, the combination of SystemVerilog’s Interface method with object-oriented testbench creation techniques enables the easy implementation of a powerful constraint-driven verification methodology. The constraints are supplied by embedded assertions that express design properties that must be proved true, or are covered during verification. Such assertions may be re-used in an SOC development that leverages design re-use and/or IP-based design. Until now, this has not been achieved easily by other implementation-level tools and languages.